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ASAHI KASEI
[AK9844A]
AK9844A
4Kbit EEPROM with 4ch 8bit D/A Converter
General Description
The AK9844A includes 4 channel, 8-bit D/A converters with on-chip output buffer amps and it is capable to store the input digital data of each D/A converter by on-chip non-volatile CMOS EEPROM. The AK9844A is optimally designed for various circuit adjustments for consumer and industrial equipments and it is ideally suited for replacing mechanical trimmers.
Features
EEPROM section 4 word x 8-bit organization (Dedicated for DAC data) 256 word x 16-bit organization (General purpose memory) Serial data interface Sequential register read Automatic write cycle 100K write cycles 10 year data retention D/A section 4 channels Resolution Differential Non-Linearity Linearity Error Output Voltage Range AUTO READ Function Power down mode
SK CS VREF1
: 8-bits : 1.0 LSB : 1.5 LSB : GND to VCC
PROTECT
Control Logic Instruction Register Data Register
Latch Decoder
-+
DI
8bit Latch
8
8bit D/A
AO0
DO
8 8
8bit Latch
8
8bit D/A
-+
AO1
VCC
8bit Latch
GND
8
8bit D/A
-+
AO2
EEPROM
4128bit 256 x 16bit + 4 x 8bit
8bit Latch
8
8bit D/A
-+
AO3
PD
VREF2
Block Diagram
DAD05E-00 -12005/03
ASAHI KASEI
[AK9844A]
Ordering Guide AK9844AV Pin Layout -40C to +85C 16-pin TSSOP
AK9844AV
GND PROTECT PD VCC NC VREF1 AO0 AO1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16pin TSSOP DI DO SK CS NC VREF2 AO3 AO2
Pin Description No. 1 2 Pin Name GND PROTECT I/O I Function Ground Pin, 0V Protect Pin "L" : Programming to the D/A Section of EEPROM is disabled. "H" : Normal operation Power-down Pin "L" : Power down mode "H" : Normal mode Power Supply Voltage Reference Input1 The analog output ranges of the AO0 and the AO1 are set by the VREF1 pin. Analog Output Pins (8-bit D/A outputs)
3
PD
I
4 6
VCC VREF1
I
7 8 9 10 11
AO0 AO1 AO2 AO3 VREF2
O
I
Voltage Reference Input1 The analog output ranges of the AO2 and the AO3 are set by the VREF2 pin. Chip Select Pin Serial Clock Pin Serial Data Output Pin Serial Data Input Pin Not Connected (Schmitt-trigger input) (Schmitt-trigger input)
13 14 15 16
CS SK DO DI
I I O I -
5, 12 NC
DAD05E-00 -2-
2005/03
ASAHI KASEI
[AK9844A]
Functional Description
The AK9844A includes the EEPROM section and the D/A converter section which consists of 4 channel, 8bit D/A converters with output buffer amps. The EEPROM section is divided into memory block and DAC register block. The capacity of the memory block is 4096bits which are organized into 256 registers of 16bits each. The DAC digital input data for D/A converters are stored in the DAC register block which is organized into 4 registers of 8bits each. The address for the memory block is "000000000" to "011111111". The address for the DAC register is "100000000" to "100000011". The configuration of the EEPROM section is showed on figure.1. The AK9844A can connect to the serial communication port of popular one chip microcontrollers directly (3 line negative clock synchronous interface). At write operation, the AK9844A takes in the write data from the DI pin to a register synchronously with rising edge of the SK pin. At read operation, the AK9844A takes out the read data from a register to the DO pin synchronously with falling edge of the SK pin. The AK9844A has 6 instructions such as READ, WRITE, WREN, WRDS, PDEN and PDDS. The each instruction is organized by op-code block(8bits), address block(8bits), and data(8bits x 2). The output of DAC is set by storing the DAC digital input data in the DAC register block. The DO pin is high impedance except that the DO pin outputs the read data and the status signal.
000000000 Memory Block 011111111 100000000 100000011 $0FF $100 $103 100000000 100000001 100000010 100000011 Digital input data for DAC (A00) Digital input data for DAC (A01) Digital input data for DAC (A02) Digital input data for DAC (A03) $100 $101 $102 $103 $000
DAC Register Block
Figure 1. Configuration of the EEPROM section
DAD05E-00 -3-
2005/03
ASAHI KASEI
[AK9844A]
Data Protection To protect against accidental data disturb, the AK9844A has programming enable state and programming disable state. In programming disable state, the programming operation is not executed. When VCC is applied to the AK9844A, the AK9844A is powered up in the programming disable mode. The programming instruction should be preceded by the WREN instruction. Once the WREN instruction is executed, the programming state remains enabled until the WRDS instruction is executed or VCC is removed from the device. Execution of the READ instruction is independent of both WREN and WRDS instructions. The AK9844A also can prohibit to program into the DAC register block by the control of the PROTECT pin. When the PROTECT pin is "L", the programming into the DAC register block is not executed.
PROTECT pin Programming State Memory Block DAC Register Block
PROTECT="H" Enable Disable x x
PROTECT="L" Enable x Disable x x
: Programming into the block is executed. x: Programming into the block is not executed. Table 1. Relation between the programming operation and the PROTECT pin
DAD05E-00 -4-
2005/03
ASAHI KASEI
[AK9844A]
Output of D/A converter The AK9844A includes 4 channel, 8bit D/A converter. The output voltage ranges for AO0 and AO1 are set by the VREF1 pin and the output voltage ranges for AO2 and AO3 are set by the VREF2 pin. The output voltage can be set by the READ or WRITE instruction. When the DAC register block is specified in the WRITE instruction, the output voltage for the specified D/A converter is set. When the WRITE instruction is executed in case that the PROTECT pin is "H" and the programming state is enabled, the output voltage for the specified D/A converter is set and the specified address in the DAC register block in EEPROM is written with the data specified in the instruction. When the WRITE instruction is executed in case that the PROTECT pin is "H" and the programming state is disabled, the output voltage for the specified D/A converter is set and the specified address in the DAC register block in EEPROM is not written with the data specified in the instruction. When the WRITE instruction is executed in case that the PROTECT pin is "L", the output voltage for the specified D/A converter is not set and the specified address in the DAC register block in EEPROM is not written with the data specified in the instruction. The relation between the WRITE instruction and the DAC register block is showed on the Table 2. When the DAC register block is specified in the READ instruction, the output voltage for the specified D/A converter is set by the data which is stored in the DAC register block in EEPROM, and the DO pin outputs the data in the specified address. Execution of the READ instruction is independent of the PROTECT pin and the programming state. PROTECT pin Programming State Enable "H" Disable Enable "L" Disable Table 2. Relation between the WRITE instruction and the DAC register block DAC register block (EEPROM section) Output of DAC (D/A Converter section)
The specified address in the The output voltage for the DAC register block is written with the data specified in the specified D/A converter is set by the data specified in the instruction. instruction. The data in the DAC register section does not change. The output of the DAC does not change.
AUTO READ Function When VCC is applied to the AK9844A, the data on EEPROM are read out and loaded at a time to each corresponding D/A (4 channels total) automatically, starting from AO0 to AO3 in ascending order. Then each D/A analog output is settled to pre-determined value. If the CS pin goes to "H" and then goes to "L" after "power-up" with the PROTECT pin and the CS pin left "L", AUTO READ cycle is initiated. After the CS pin goes to "L", 4 channel D/A outputs are settled to pre-determined value within 2ms. In AUTO READ cycle, the SK pin and the DI pin become "don't care" and the serial data do not output. If the WREN instruction is executed after AUTO READ cycle is completed, programming into the memory block on the internal EEPROM is enabled.
DAD05E-00 -52005/03
ASAHI KASEI
[AK9844A]
Instruction and Data Format The instructions consist of op-code(8bits), address(8bits) and data(8bits x 2). the instruction and data set at WRITE execution.
First MSB 1 0 1 0 0 1 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 Last LSB D2 D1 D0
The followings are
Op-code Address
A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 1 0 1 DAC Register Block Data for A00 Data for A01 Data for A02 Data for A03 Memory Block Function
Data
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X D/A Output Voltage ( VREF / 256 ) ( VREF / 256 ) ( VREF / 256 ) VREF x1 x2 x255
DAD05E-00 -6-
2005/03
ASAHI KASEI
[AK9844A]
Power Down Function There are the power down mode and the normal mode in AK9844A. When the AK9844A is in power down mode, the outputs of D/A are "High impedance" and the DAC section is in the standby mode and the power consumption of the AK9844A is decreased. The power down mode of AK9844A can be determined by the control of the PD pin or the PDEN/PDDS instructions. When the PD pin is low level, the AK9844A is in power down mode. When the PD pin is high level, the state of the AK9844A can be determined by PDEN/PDDS instructions. When the PD pin is High level and the PDEN instruction is executed, the AK9844A becomes the power down mode. Once the AK9844A becomes the power down mode, the AK9844A is in the power down mode until the PDDS instruction is executed. When the PDDS instruction is executed, the AK9844A becomes the normal mode. If the CS pin is High level in the power down mode, the EEPROM section also becomes the standby mode and the AK9844A becomes the lower power-down mode. The relation between the PD pin and the PDEN/PDDS instructions is showed on Table 3. The relation between the power down mode and the DAC/EEPROM section is showed on Table 4. The state at the time AK9844A is powered up is showed on Table 5. PD pin Low level High level instruction PDEN PDDS PDEN PDDS mode power down mode power down mode normal mode
Table 3. Relation between the PD pin and the PDEN/PDDS instructions State normal mode power down mode1 power down mode2 DAC section normal mode standby mode standby mode EEPROM section normal mode normal mode standby mode
CS pin="L" CS pin="H"
Table 4. Relation between the power down mode and the DAC/EEPROM section Condition at the time AK9844A is powered on CS pin="L" PD pin="L" CS pin="H" PD pin="H" State power down mode1 power down mode2 normal mode
Table 5. State at the time AK9844A is powered up Precautions for use 1) Output voltage of D/A converter at the time the AK9844A is powered up At the time the AK9844A is powered up, the D/A converters output "VREF/2" until the instruction or AUTO READ is executed. 2) Power Supply Decoupling On the boards, decoupling capacitors(0.1F) between power supply pins(VCC,VREF1,VREF2) and GND should be located as near as possible to the part.
DAD05E-00 -7-
2005/03
ASAHI KASEI
[AK9844A]
Instruction Set
The AK9844A has 6 instructions such as READ, WRITE, WREN, WRDS, PDEN, PDDS. Each instruction consists of Op-code, address and data. The instruction set is showed on Table 6. When the instructions are executed consecutively, the CS pin should be brought to high level for a minimum of 250ns(tCS) between consecutive instruction cycle. Instruction READ WRITE WREN WRDS PDEN PDDS Op-code 1010100 1010010 1010001 1010000 1010110 1010011 A8 A8 1 0 0 0 Address A7 A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Table 6. Instruction set WRITE The WRITE instruction is followed by 16 bits of data to be written into the specified address. After the 32nd rising edge of SK to read DO in, the AK9844A will be put into the automatic write time-out period. During the automatic write time-out period (Busy status), the CS pin need not be high level. The DO pin indicates the Ready/Busy status of the EEPROM in AK9844A. After the 32nd rising edge of SK to read DO in, the AK9844A will be put into the automatic write time-out period. When the automatic write time-out period start, the DO pin outputs the Ready/Busy status. When the DO pin outputs low level, the AK9844A is in the automatic write time-out and the next instruction can not be accepted. When the DO pin outputs high level, the automatic write time-out period has ended and the AK9844A is ready for a next instruction. When the CS pin is changed to high level after confirmation of Ready/Busy signal on the DO pin, the DO pin becomes "Hi-Z". The Ready/Busy signal can be confirmed until the initial 1 bit of the next instruction inputs from the execution of the WRITE instruction.
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 31 32
Data D15-D0 D15-D0 X X X X
Comments Read register Write register Write enable Write disable Power down enable Power down disable X: Don't care
SK DI DO
1 0 1 0 0 1 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 Hi-Z Status output (READY), if previous instruction is WRITE.
D1 D0
BUSY tE/W
READY
WRITE instruction
DAD05E-00 -8-
2005/03
ASAHI KASEI
[AK9844A]
READ The read instruction is the only instruction which outputs serial data on the DO pin. After a read instruction is received, the instruction and address are decoded, followed by data transfer from the memory register into a 16 bit serial-out shift register. When the 17th falling edge of SK is received, the DO pin will come out of high impedance state and shift out the data from D15 first in descending order which is located at the address specified in the instruction. Sequential register read The data in the next address can be read sequentially to provide clock. The memory automatically cycles to the next register after each 16 data bits are clocked out. The sequential register read function is effective for address: A7~A0. When the highest address is reached ($0FF/$103), the address counter rolls over to address $000/$100 allowing the read cycle to be continued indefinitely.
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 31 32 33 34 35
SK DI DO
1 0 1 0 1 0 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 Hi-Z Status output (READY), if previous instruction is WRITE. Hi-Z
D15 D14 D13
D1 D0 D15 D14 D13
1st Data
2nd Data
READ instruction
WREN / WRDS When VCC is applied to the part, it powers up in the programming disable(WRDS) state. Programming must be preceded by a programming enable(WREN) instruction. Programming remains enabled until a programming disable(WRDS) instruction is executed or VCC is removed from the part. The programming disable instruction is provided to protect against accidental data disturb. Execution of a read instruction is not affected by both WREN and WRDS instruction.
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SK DI DO
Status output (READY), if previous instruction is WRITE. 1 0 1 0 0 0
WREN=11 WRDS=00
X
X
X
X
X
X
X
X
Hi-Z
WREN / WRDS instruction
DAD05E-00 -9-
2005/03
ASAHI KASEI
[AK9844A]
PDEN / PDDS The AK9844A has the power-down mode and the normal mode. When the PDEN instruction is executed while the PD pin is high level, the AK9844A becomes the power-down mode. The AK9844A is in the power-down mode until PDDS instruction is executed. After the PDDS instruction is executed, the AK9844A changed to normal mode from power-down mode. In case that the PD pin is low level, the PDEN/PDDS instructions are invalid and are not executed.
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SK DI DO
1 0 1 0 1 1 0 0 X X X X X X X X
Hi-Z Status output (READY), if previous instruction is WRITE.
PDEN instruction
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SK DI DO
1 0 1 0 0 1 1 0 X X X X X X X X
Hi-Z Status output (READY), if previous instruction is WRITE.
PDDS instruction
DAD05E-00 - 10 -
2005/03
ASAHI KASEI
[AK9844A]
Absolute Maximum Ratings
Parameter Power Supply Input Voltage Ambient Temperature Storage Temperature Symbol VCC VIO Ta Tst Condition Relative to GND Relative to GND Min -0.6 -0.6 -40 -65 Max +7.0 VCC+0.6 +85 +150 Unit V V C C
Recommended Operating Condition
Parameter Power Supply Analog Output Load Capacitance Symbol VCC1 VCC2 AOC Condition DAC operation EEPROM operation Min 2.7 1.8 Typ Max 5.5 5.5 100 Unit V V pF
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2005/03
ASAHI KASEI
[AK9844A]
Electrical Characteristics
D.C. ELECTRICAL CHARACTERISTICS ( 1.8V VCC 5.5V, GND=0V, -40C Ta 85C, unless otherwise specified ) Parameter Power Consumption Symbol IDD1 IDD2 IDD3 (Note1, Note2) Input High Voltage1 CS, SK, PROTECT pin Input High Voltage2 PD, DI pin Input Low Voltage1 CS, SK, PROTECT pin Input Low Voltage2 PD, DI pin Output High Voltage Output Low Voltage IDD4 VIH1 VIH2 VIH3 VIL1 VIL2 VIL3 VOH VOL1 VOL2 Input Leakage 3 State Leakage Current ILI IOZ 2.2V VCC 5.5V 1.8V VCC < 2.2V IOH=-50A 2.2V VCC 5.5V IOL=1.0mA 1.8V VCC < 2.2V IOL=0.1mA VIN=VCC CS="H" VCC-0.3 0.4 0.4 1.0 1.0 2.2V VCC 5.5V 1.8V VCC < 2.2V Condition Normal mode WRITE, 1/tSKP=2MHz Normal mode READ, 1/tSKP=2MHz Power down mode1 READ, 1/tSKP=2MHz Power down mode2 0.8xVCC 0.7xVCC 0.8xVCC 0.2xVCC 0.3xVCC 0.2xVCC Min. Typ. Max. 6.5 3.3 0.75 0.8 Unit mA mA mA A V V V V V V V V V A A
Note1 : VCC=5.5V, VIN=VCC/GND, DO=OPEN Note2 : Please refer to "Power Down Function" regarding power down mode.
DAD05E-00 - 12 -
2005/03
ASAHI KASEI
[AK9844A]
A.C. ELECTRICAL CHARACTERISTICS 1) EEPROM section ( 1.8V VCC 5.5V, GND=0V, -40C Ta 85C, unless otherwise specified ) Parameter Symbol Condition Min. Typ. Max. Unit SK Cycle Time tSKP1 500 ns 2.5V VCC 5.5V tSKP2 SK Pulse Width tSKW1 tSKW2 SK High Pulse Width (Note3) CS Setup Time CS Hold Time tSKH1 tSKH2 tSKH3 tCSS tCSH1 tCSH2 SK Setup Time Data Setup Time tSKS tDIS1 tDIS2 tDIS3 Data Hold Time tDIH1 tDIH2 tDIH3 Data Output Delay (READ) tPD1 tPD2 tPD3 (Note5) Data Output Delay (RDY/BUSY) (Note5) Selftimed Programming Time Write Recovery Time Min CS High Time DO High-Z Time tPD4 tPD tE/W1 tE/W2 tRC tCS tOZ 2.5V VCC 5.5V 1.8V VCC < 2.5V 100 250 500 4.0V VCC 5.5V 2.5V VCC < 4.0V 1.8V VCC < 2.5V 4.0V VCC 5.5V 2.5V VCC < 4.0V 1.8V VCC < 2.5V 4.0V VCC 5.5V 2.5V VCC < 4.0V 2.2V VCC < 2.5V 1.8V VCC < 2.2V READ, WREN, WRDS, PDEN, PDDS WRITE (Note4) 1.8V VCC < 2.5V 2.5V VCC 5.5V 1.8V VCC < 2.5V 4.0V VCC 5.5V 2.5V VCC < 4.0V 1.8V VCC < 2.5V 1.5 250 750 250 500 750 100 100 1000 100 100 150 200 100 150 200 150 250 300 500 1000 7 10 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns
Note3 : tSKH is the high pulse width of 16th SK pulse in READ operation. When the data in the next address are read sequentially by continuing to provide clock, tSKH are applied to the high pulse width of 32nd and 48th (multiple of 16) SK pulse in READ operation. Note4 : In case that the data of the DAC section is not changed and the output of the DAC is changed, tCSH is min. 1s. In case of the other WRITE instruction, tCSH is min. 100ns. Note5 : CL=100pF
DAD05E-00 - 13 2005/03
ASAHI KASEI
[AK9844A]
2) DAC section ( 2.7V VCC 5.5V, GND=0V, -40C Ta 85C, unless otherwise specified ) Parameter D/A Reference Voltage A0, A1 A2, A3 D/A Reference Current Resolution Differential Non-Linearity Integral Non-Linearity (Note7) Error for Input data "00" (Note6) Error for Input data "FF" (Note6) Buffer-AMP Output Voltage Range(1) 3.6V VCC 5.5V (Note8) Buffer-AMP Output Voltage Range(2) 2.7V VCC < 3.6V Setup Time in AUTO READ D/A Settling Time (CL=100pF) Symbol VREF1 VREF2 IREF DNL NL EZERO EFULL VAO1 VAO2 VAO3 VAO4 VAO5 tARS tLDD1 tLDD2 3.6V VCC 5.5V 2.7V VCC < 3.6V |IAO| = 0A |IAO| 200A |IAO| 1mA |IAO| = 0A |IAO| 500A 0.1 0.2 0.3 0.1 0.3 500 100 200 400 Condition Min. 2.7 2.7 VREF=5.0V Monotonicity VCC=VREF=5.0V 1LSB=VREF/256 IAO=0.0A CL=100pF 200 -1 -1.5 0 0 Typ. Max. VCC VCC 400 8 +1 +1.5 +0.1 +0.1 VCC-0.1 VCC-0.2 VCC-0.3 VCC-0.1 VCC-0.3 Unit V V A bit LSB LSB V V V V V V V s s s
Note6 : Please refer to the Figure 2. Note7 : Integral Non-Linearity is the error between the actual line and the ideal line. The ideal line exhibits a perfect linear DAC output characteristics between the input digital data "00" and the input digital data "FF". Note8 : VCC=VREF * Please refer to "Instruction and Data Format" regarding the relation between input digital data and DAC output voltage.
DAC Output Voltage 5.0V
VCC=VREF=5V CL=100pF
5.0V EZERO 00 FF EFULL
00
FF
Input digital data
Figure 2. DAC output characteristics (IAO=0.0A)
DAD05E-00 - 14 2005/03
ASAHI KASEI
[AK9844A]
Timing Waveform
tCS
tCSS tSKP
CS
tSKS tSKW
tSKW
SK
tDIS tDIH
DI
tRC
1
0
1
DO
Hi-Z
Input Waveform
CS
tSKH tCSH
SK DI DO
16
A0
tPD tOZ
D15
D2
D1
D0
tLDD
D/A
Waveform in READ instruction
DAD05E-00 - 15 -
2005/03
ASAHI KASEI
[AK9844A]
CS
tCSH
SK DI
D2 D1 D0
tLDD
D/A
Programming Waveform in WRITE instruction
CS SK DI DO
tLDD
D0
tPD tE/W tOZ
BUSY
READY
D/A
Status Output (Note) In case that the data of the DAC section is not changed and the output of the DAC is changed, Ready/Busy signal does not output on DO pin.
VCC
tARS min. 2ms
CS PROTECT AO0 (D/A OUT) : AO3 (D/A OUT)
Waveform in AUTO READ
DAD05E-00 - 16 2005/03
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

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